Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Transforming Binary Code for Low-Power Embedded Processors., and . IEEE Micro, 24 (3): 21-33 (2004)Efficient Construction of Aliasing-Free Compaction Circuitry., and . IEEE Micro, 22 (5): 82-92 (2002)Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions., and . Design Autom. for Emb. Sys., 14 (3): 309-326 (2010)The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations., and . IEEE Trans. Computers, 54 (1): 61-75 (2005)Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs., and . IEEE Trans. Computers, 52 (11): 1480-1489 (2003)Automatic Synthesis of Self-Recovering VLSI Systems., and . IEEE Trans. Computers, 45 (2): 131-142 (1996)Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection., and . IEEE Trans. VLSI Syst., 20 (12): 2170-2183 (2012)Hierarchical Modeling of the VLSI Design Process., , and . IEEE Expert, 6 (2): 56-70 (1991)Reducing Average and Peak Test Power Through Scan Chain Modification., , and . J. Electronic Testing, 19 (4): 457-467 (2003)On the identification of modular test requirements for low cost hierarchical test path construction., and . Integration, 40 (3): 315-325 (2007)