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ITAC: A complete 3D integration test platform.

D. Lattard, L. Arnaud, A. Garnier, N. Bresson, F. Bana, R. Segaud, A. Jouve, H. Jacquinot, S. Moreau, K. Azizi-Mourier, C. Chantre, P. Vivet, G. Pillonnet, F. Casset, F. Ponthenier, A. Farcy, S. Lhostis, J. Michailos, A. Arriordaz, and S. Cheramy. 3DIC, page 1-4. IEEE, (2016)

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Advanced 3D Technologies and Architectures for 3D Smart Image Sensors.P. Vivet, G. Sicard, L. Millet, S. Chevobbe, K. Chehida, L. Cubero, M. Alegre, M. Bouvier, A. Valentian, M. Lepecq and 7 other author(s). DATE, page 674-679. IEEE, (2019)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro-Panades, C. Tortolero, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.P. Coudrain, P. Souare, R. Prieto, V. Fiori, A. Farcy, L. Le-Pailleur, J. Colonna, C. Santos, P. Vivet, M. Jamaa and 6 other author(s). IEEE Design & Test, 33 (3): 21-36 (2016)A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.E. Guthmuller, C. Tortolero, P. Vivet, C. Bernard, I. Panades, J. Durupt, E. Beignc, D. Lattard, S. Cheramy, A. Greiner and 2 other author(s). ESSCIRC, page 318-321. IEEE, (2018)A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.P. Vivet, Y. Thonnart, R. Lemaire, C. Santos, E. Beigné, C. Bernard, F. Darve, D. Lattard, I. Panades, D. Dutoit and 9 other author(s). J. Solid-State Circuits, 52 (1): 33-49 (2017)IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Tortolero, I. Miro-Panades, G. Moritz, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)3D integration demonstration of a wireless product with design partitioning.G. Druais, P. Ancey, C. Aumont, V. Caubet, L. Chapelon, C. Chaton, S. Cheramy, S. Cordova, E. Cirot, J. Colonna and 17 other author(s). 3DIC, page 1-5. IEEE, (2011)Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement.A. Jouve, Y. Sinquin, A. Garnier, M. Daval, P. Chausse, M. Argoud, N. Allouti, L. Baud, J. Dechamp, R. Franiatte and 3 other author(s). 3DIC, page TS1.4.1-TS1.4.8. IEEE, (2015)8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.P. Vivet, Y. Thonnart, R. Lemaire, E. Beigné, C. Bernard, F. Darve, D. Lattard, I. Panades, C. Santos, F. Clermidy and 4 other author(s). ISSCC, page 146-147. IEEE, (2016)Which interconnects for which 3D applications? Status and perspectives.Y. Lamy, J. Colonna, G. Simon, P. Leduc, S. Cheramy, and C. Laviron. 3DIC, page 1-6. IEEE, (2013)

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Disambiguation of "Cheramy, Séverine"

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ITAC: A complete 3D integration test platform.

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Disambiguation of "Cheramy, Séverine"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML ITAC: A complete 3D integration test platform.

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ITAC: A complete 3D integration test platform.