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b Robust and Fault Tolerant Asynchronous 3D Links.

P. Vivet, Y. Thonnart, R. Lemaire, C. Santos, E. Beigné, C. Bernard, F. Darve, D. Lattard, I. Panades, D. Dutoit, F. Clermidy, S. Cheramy, A. Sheibanyrad, F. Pétrot, E. Flamand, J. Michailos, A. Arriordaz, L. Wang, and J. Schloeffel. J. Solid-State Circuits, 52 (1): 33-49 (2017)

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Architecture massivement parallèle : un réseau de cellules intégré pour la reconstruction d'images. (Massively parallel architecture : and integrated cellular network for image reconstruction).D. Lattard. Grenoble Institute of Technology, France, (1989)A 3D reconfigurable platform for 4G telecom applications.W. Lafi, D. Lattard, and A. Jerraya. DATE, page 555-558. IEEE, (2011)3D advanced integration technology for heterogeneous systems.P. Vivet, C. Bernard, F. Clermidy, D. Dutoit, E. Guthmuller, I. Panades, G. Pillonnet, Y. Thonnart, A. Garnier, D. Lattard and 4 other author(s). 3DIC, page FS6.1-FS6.3. IEEE, (2015)Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning.I. Jani, D. Lattard, P. Vivet, J. Durupt, S. Thuries, and E. Beigné. ETS, page 1-2. IEEE, (2019)An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip.W. Lafi, D. Lattard, and A. Jerraya. Softw., Pract. Exper., 42 (7): 877-890 (2012)Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations.O. Billoint, K. Azizi-Mourier, G. Cibrario, D. Lattard, M. Mouhdach, S. Thuries, and P. Vivet. 3DIC, page 1-5. IEEE, (2019)An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs.V. Lenoir, D. Lattard, and A. Jerraya. ISCAS, page 1222-1225. IEEE, (2015)High level modelling and performance evaluation of address mapping in NAND flash memory.W. Lafi, D. Lattard, and A. Jerraya. ICECS, page 659-662. IEEE, (2009)Trends in complex SoC Design: From technology variability to multiprocessor architectures.D. Lattard. ICECS, page 1. IEEE, (2007)A VLSI implementation of parallel image reconstruction.D. Lattard, and G. Mazaré. CVGIP: Graphical Model and Image Processing, 53 (6): 581-591 (1991)

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A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.

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URL
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APA
Chicago
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A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.