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Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.

P. Coudrain, P. Souare, R. Prieto, V. Fiori, A. Farcy, L. Le-Pailleur, J. Colonna, C. Santos, P. Vivet, M. Jamaa, D. Dutoit, F. de Crecy, S. Dumas, C. Chancel, D. Lattard, and S. Cheramy. IEEE Design & Test, 33 (3): 21-36 (2016)

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Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes.C. Santos, P. Vivet, S. Thuries, O. Billoint, J. Colonna, P. Coudrain, and L. Wang. 3DIC, page 1-5. IEEE, (2016)Thermal correlation between measurements and FEM simulations in 3D ICs.P. Souare, F. de Crecy, V. Fiori, M. Jamaa, A. Farcy, S. Gallois-Garreignot, A. Borbely, J. Colonna, P. Coudrain, B. Giraud and 4 other author(s). 3DIC, page 1-6. IEEE, (2013)Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.P. Coudrain, P. Souare, R. Prieto, V. Fiori, A. Farcy, L. Le-Pailleur, J. Colonna, C. Santos, P. Vivet, M. Jamaa and 6 other author(s). IEEE Design & Test, 33 (3): 21-36 (2016)Chip to wafer copper direct bonding electrical characterization and thermal cycling.Y. Beilliard, P. Coudrain, L. Cioccio, S. Moreau, L. Sanchez, B. Montmayeul, T. Signamarcheix, R. Estevez, and G. Parry. 3DIC, page 1-7. IEEE, (2013)IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, C. Tortolero, I. Miro-Panades, G. Moritz, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS.P. Batude, T. Ernst, J. Arcamone, G. Arndt, P. Coudrain, and P. Gaillardon. IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (4): 714-722 (2012)Thermal performance of 3D ICs: Analysis and alternatives.C. Santos, P. Vivet, J. Colonna, P. Coudrain, and R. da Luz Reis. 3DIC, page 1-7. IEEE, (2014)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters.P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro-Panades, C. Tortolero, J. Durupt, C. Bernard, D. Varreau and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)3D integration demonstration of a wireless product with design partitioning.G. Druais, P. Ancey, C. Aumont, V. Caubet, L. Chapelon, C. Chaton, S. Cheramy, S. Cordova, E. Cirot, J. Colonna and 17 other author(s). 3DIC, page 1-5. IEEE, (2011)Advances toward reliable high density Cu-Cu interconnects by Cu-SiO2 direct hybrid bonding.Y. Beilliard, S. Moreau, L. Cioccio, P. Coudrain, G. Romano, A. Nowodzinski, F. Aussenac, P. Jouneau, E. Rolland, and T. Signamarcheix. 3DIC, page 1-8. IEEE, (2014)

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Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.

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Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.