Author of the publication

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.

, , , , , , , , , , , and . ESSCIRC, page 318-321. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols., , , and . ARCS, volume 10172 of Lecture Notes in Computer Science, page 111-123. Springer, (2017)3D advanced integration technology for heterogeneous systems., , , , , , , , , and 4 other author(s). 3DIC, page FS6.1-FS6.3. IEEE, (2015)Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach., , and . ASAP, page 1-8. IEEE Computer Society, (2018)3D integration for power-efficient computing., , and . DATE, page 779-784. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Adaptive Stackable 3D Cache Architecture for Manycores., , and . ISVLSI, page 39-44. IEEE Computer Society, (2012)Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects., , , , , and . ISVLSI, page 615-620. IEEE Computer Society, (2015)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)3D stacking for multi-core architectures: From WIDEIO to distributed caches., , , , and . ISCAS, page 537-540. IEEE, (2013)Architectural exploration of a fine-grained 3D cache for high performance in a manycore context., , and . VLSI-SoC, page 302-307. IEEE, (2013)A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches., , , , , , , , , and 2 other author(s). ESSCIRC, page 318-321. IEEE, (2018)