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Resistive Memory-Based In-Memory Computing: From Device and Large-Scale Integration System Perspectives.

B. Yan, B. Li, X. Qiao, C. Xue, M. Chang, Y. Chen, und H. Li. Adv. Intell. Syst., 1 (7): 1900068 (2019)

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Univ. -Prof. Achim Menges University of Stuttgart

ABxM.MultiStorey.Columns: Agent-based Column Arrangement for Multi-Storey StructuresL. Orozco, L. Siriwardena, und A. Menges. Software, (2024)

ABxM.MultiStorey.Columns: Agent-based Column Arrangement for Multi-Storey StructuresL. Orozco, L. Siriwardena, und A. Menges. Software, (2024)Timber Column Slab SolverK. Udaykumar, L. Orozco, A. Krtschil, A. Menges, und J. Knippers. Software, (2024)Related to: Udaykumar, K., Orozco, L., Krtschil, A., Menges, A., & Knippers, J. (2023). Interactive gradient-decent optimization method for timber column-slab structures. In Proceedings of IASS Annual Symposia, IASS 2023 Melbourne Symposium: Optimisation methods and applications. International Association for Shell and Spatial Structures (IASS). url: https://www.ingentaconnect.com/contentone/iass/piass/2023/00002023/00000008/art00010.Reinforcement Arrangement DataL. Orozco, A. Krtschil, L. Skoury, J. Knippers, und A. Menges. Dataset, (2024)Related to: Orozco, L., Krtschil, A., Skoury, L., Knippers, J., & Menges, A. (2022). Arrangement of reinforcement in variable density timber slab systems for multi-story construction. International Journal of Architectural Computing, vol. 20, no. 4, pp. 707-727. doi: 10.1177/14780771221135003.

Kuan Meng University of Stuttgart

Dr. Sisi Fan University of Stuttgart

Raphael Menges University of Stuttgart

Nicola Fanton University of Stuttgart

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Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems.M. Chang, S. Yang, und K. Chen. IEEE Trans. on Circuits and Systems, 56-I (8): 1657-1667 (2009)Crosstalk-insensitive via-programming ROMs using content-aware design framework.M. Chang, L. Chiou, und K. Wen. IEEE Trans. on Circuits and Systems, 53-II (6): 443-447 (2006)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.J. Wu, Y. Chen, M. Chang, P. Chou, C. Chen, H. Liao, M. Chen, Y. Chu, W. Wu, und H. Yamauchi. J. Solid-State Circuits, 46 (4): 815-827 (2011)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements.M. Chang, S. Yang, C. Liang, C. Chiang, P. Chiu, und K. Lin. J. Solid-State Circuits, 45 (10): 2142-2155 (2010)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_TH$ Read-Port, and Offset Cell VDD Biasing Techniques.M. Chang, M. Chen, L. Chen, S. Yang, Y. Kuo, J. Wu, H. Su, Y. Chu, W. Wu, T. Yang und 1 andere Autor(en). J. Solid-State Circuits, 48 (10): 2558-2569 (2013)SRAM Cell Current in Low Leakage Design.D. Kwai, C. Hsiao, C. Kuo, C. Chuang, M. Hsu, Y. Chen, Y. Sung, H. Pan, C. Lee, M. Chang und 1 andere Autor(en). MTDT, Seite 65-70. IEEE Computer Society, (2006)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.M. Chang, C. Lin, A. Lee, C. Kuo, G. Yang, H. Tsai, T. Chen, S. Sheu, P. Tseng, H. Lee und 1 andere Autor(en). ISSCC, Seite 1-3. IEEE, (2015)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.M. Chen, L. Chen, M. Chang, S. Yang, Y. Kuo, J. Wu, M. Ho, H. Su, Y. Chu, W. Wu und 2 andere Autor(en). VLSIC, Seite 112-113. IEEE, (2012)A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing.M. Chang, L. Huang, W. Lin, Y. Chiang, C. Kuo, C. Chuang, K. Yang, H. Tsai, T. Chen, und S. Sheu. J. Solid-State Circuits, 51 (11): 2786-2798 (2016)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.Z. Wang, Y. Liu, A. Lee, F. Su, C. Lo, Z. Yuan, J. Li, C. Lin, W. Chen, H. Chiu und 7 andere Autor(en). J. Solid-State Circuits, 52 (10): 2769-2785 (2017)