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Disambiguation of "Geuskens, Bibiche M."

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Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.

, , , , and . CICC, page 1-4. IEEE, (2010)

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M. Nudischer

M. Kratzer

M. Liewald

M. Fittingho

M. Christmann

 

Other publications of authors with the same name

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops., , , , , , , , , and 1 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 208-217 (2011)Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays., , , , , , , and . J. Solid-State Circuits, 46 (4): 797-805 (2011)Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency., , , , , , , , , and . CICC, page 1-4. IEEE, (2010)A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS., , , , , , and . J. Solid-State Circuits, 49 (4): 917-927 (2014)PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction., , , , , , , , and . ISSCC, page 352-353. IEEE, (2010)A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip., , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (8-A): 760-771 (2013)A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 46 (1): 194-208 (2011)All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control., , , , , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2017-2025 (2011)Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM., , , , , and . ISSCC, page 234-236. IEEE, (2012)A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance., , , , , , , , , and 1 other author(s). ISSCC, page 282-283. IEEE, (2010)