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Disambiguation of "Niar, Smaïl"

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A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.

, , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (8-A): 760-771 (2013)

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Other publications of authors with the same name

Optimal sample length for efficient cache simulation., , and . Journal of Systems Architecture, 51 (9): 513-525 (2005)Scalable row-based parallel H.264 decoder on embedded multicore processors., , , and . Signal, Image and Video Processing, 9 (Supplement-1): 57-71 (2015)Efficient FPGA implementation of H.264 CAVLC entropy decoder., , , , and . IDT, page 1-3. IEEE, (2013)A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC., , , , and . DSD, page 3-10. IEEE Computer Society, (2009)Adaptive Sampling for Efficient MPSoC Architecture Simulation., , and . MASCOTS, page 186-192. IEEE Computer Society, (2007)Rapid Performance and Power Consumption Estimation Methods for Embedded System Design., and . IEEE International Workshop on Rapid System Prototyping, page 47-53. IEEE Computer Society, (2006)A WCET-aware cache coloring technique for reducing interference in real-time systems., , , and . CoRR, (2019)Power optimization techniques for associative processors., , , and . Journal of Systems Architecture - Embedded Systems Design, (2018)Reconfigurable Hardened Latch and Flip-Flop for FPGAs., , , and . ISVLSI, page 433-438. IEEE Computer Society, (2017)A new memory reliability technique for multiple bit upsets mitigation., , , and . CF, page 145-152. ACM, (2019)