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PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.

A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T. Karnik, S. Lu, V. De, and M. Khellah. ISSCC, page 352-353. IEEE, (2010)

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Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.S. Motaman, S. Ghosh, and J. Kulkarni. JETC, 14 (1): 8:1-8:17 (2018)Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design.J. Kulkarni, and T. Wenisch. IEEE Design & Test, 35 (6): 94-95 (2018)Improving multi-core performance using mixed-cell cache architecture.S. Khan, A. Alameldeen, C. Wilkerson, J. Kulkarni, and D. Jiménez. HPCA, page 119-130. IEEE Computer Society, (2013)Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.J. Kulkarni, B. Geuskens, T. Karnik, M. Khellah, J. Tschanz, and V. De. ISSCC, page 234-236. IEEE, (2012)Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.B. Geuskens, M. Khellah, J. Kulkarni, T. Karnik, and V. De. CICC, page 1-4. IEEE, (2010)17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.J. Keane, J. Kulkarni, K. Koo, S. Nalam, Z. Guo, E. Karl, and K. Zhang. ISSCC, page 308-309. IEEE, (2016)Resilient design in scaled CMOS for energy efficiency.J. Tschanz, K. Bowman, M. Khellah, C. Wilkerson, B. Geuskens, D. Somasekhar, A. Raychowdhury, J. Kulkarni, C. Tokunaga, S. Lu and 2 other author(s). ASP-DAC, page 625. IEEE, (2010)Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.M. Alioto, M. Abadir, T. Arslan, C. Boon, A. Burg, C. Chang, M. Chang, Y. Chang, P. Chen, P. Corsonello and 47 other author(s). IEEE Trans. VLSI Syst., 27 (2): 253-280 (2019)A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.R. Jain, B. Geuskens, S. Kim, M. Khellah, J. Kulkarni, J. Tschanz, and V. De. J. Solid-State Circuits, 49 (4): 917-927 (2014)Design for test and reliability in ultimate CMOS.M. Nicolaidis, L. Anghel, N. Zergainoh, Y. Zorian, T. Karnik, K. Bowman, J. Tschanz, S. Lu, C. Tokunaga, A. Raychowdhury and 4 other author(s). DATE, page 677-682. IEEE, (2012)

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PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.

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PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.