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Improving multi-core performance using mixed-cell cache architecture.

, , , , and . HPCA, page 119-130. IEEE Computer Society, (2013)

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Decoupled dynamic cache segmentation., , and . HPCA, page 235-246. IEEE Computer Society, (2012)Decoupled Cache Segmentation: Mutable Policy with Automated Bypass., and . PACT, page 212. IEEE Computer Society, (2011)Adaptive-Latency DRAM (AL-DRAM)., , , , , , and . CoRR, (2016)Improving cache performance using read-write partitioning., , , , and . HPCA, page 452-463. IEEE Computer Society, (2014)Programming for Non-Volatile Main Memory Is Hard., , , and . APSys, page 13:1-13:8. ACM, (2017)PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM., , and . DSN, page 239-250. IEEE Computer Society, (2016)Improving multi-core performance using mixed-cell cache architecture., , , , and . HPCA, page 119-130. IEEE Computer Society, (2013)Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost., , , , and . TACO, 12 (4): 63:1-63:29 (2016)Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins., , , , , , and . CoRR, (2018)Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance., , , , , , , , and . CoRR, (2018)