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Disambiguation of "Datta, Ramyanshu"

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Delay fault testing and silicon debug using scan chains.

, , and . European Test Symposium, page 46-51. IEEE Computer Society, (2004)

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Other publications of authors with the same name

Performance-Optimized Design for Parametric Reliability., , , , and . J. Electronic Testing, 24 (1-3): 129-141 (2008)Delay fault testing and silicon debug using scan chains., , and . European Test Symposium, page 46-51. IEEE Computer Society, (2004)Testing and debugging delay faults in dynamic circuits., , , and . ITC, page 10. IEEE Computer Society, (2005)Controllability of Static CMOS Circuits for Timing Characterization., , , , and . J. Electronic Testing, 24 (5): 481-496 (2008)Path-RO: a novel on-chip critical path delay measurement under process variations., , and . ICCAD, page 640-646. IEEE Computer Society, (2008)A Scheme for On-Chip Timing Characterization., , , and . VTS, page 24-29. IEEE Computer Society, (2006)Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing., , , , and . ITC, page 1118-1127. IEEE Computer Society, (2004)On-chip delay measurement for silicon debug., , , and . ACM Great Lakes Symposium on VLSI, page 145-148. ACM, (2004)On-Chip Delay Measurement Based Response Analysis for Timing Characterization., , , , , and . J. Electronic Testing, 26 (6): 599-619 (2010)A low latency and low power dynamic Carry Save Adder., , , , , , , and . ISCAS (2), page 477-480. IEEE, (2004)