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Controllability of Static CMOS Circuits for Timing Characterization.

, , , , and . J. Electronic Testing, 24 (5): 481-496 (2008)

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Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing., , , , and . ITC, page 1118-1127. IEEE Computer Society, (2004)Flexible module generation in the FACE design environment., , , and . ICCAD, page 396-399. IEEE Computer Society, (1988)Nand Flash Memory - Product Trends, Technology Overview, and Technical Challenges.. Asian Test Symposium, page 463. IEEE Computer Society, (2011)FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development., , , , , , and . DAC, page 466-471. ACM Press, (1989)An accurate functional level concurrent fault simulator., and . DAC, page 210-217. ACM/IEEE, (1980)Analog Compilation Based on Successive Decompositions., , and . DAC, page 369-375. (1988)Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs., and . ICCD, page 212-215. IEEE Computer Society, (1991)Constrained conditional resource sharing in pipeline synthesis., , , and . ICCAD, page 52-55. IEEE Computer Society, (1988)Impact of SoC power management techniques on verification and testing., , , , and . ISQED, page 692-695. IEEE Computer Society, (2009)High-Level Graphical User Interface Management in the FACE Synthesis Environment., , , , , and . DAC, page 549-554. ACM Press, (1989)