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Testing and debugging delay faults in dynamic circuits., , , and . ITC, page 10. IEEE Computer Society, (2005)Early-stage power grid analysis for uncertain working modes., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (5): 676-682 (2005)Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation., , , , , , and . IEEE Trans. VLSI Syst., 18 (4): 666-670 (2010)Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues., , , and . ASP-DAC, page 7-16. IEEE, (2012)A Linear-Centric Simulation Framework for Parametric Fluctuations., , and . DATE, page 568-575. IEEE Computer Society, (2002)Hierarchical Multialgorithm Parallel Circuit Simulation., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (1): 45-58 (2011)A Methodology for Worst-Case Analysis of Integrated Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 5 (1): 104-113 (1986)Simultaneous Layout Migration and Decomposition for Double Patterning Technology., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (2): 284-294 (2011)A Design Model for Random Process Variability., , , , and . ISQED, page 734-737. IEEE Computer Society, (2008)SRAM Local Bit Line Access Failure Analyses., , , , , and . ISQED, page 204-209. IEEE Computer Society, (2006)