PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Lari, Vahid"

Author of the publication

copydeleteadd this publication to your clipboard
System integration of tightly-coupled processor arrays using reconfigurable buffer structures.

, , , , and . Conf. Computing Frontiers, page 2:1-2:4. ACM, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Vahid Pourostad University of Stuttgart

Samaneh Vahid Dastjerdi University of Stuttgart

Raoul Laribi University of Stuttgart

Dr. Vahid Aref University of Stuttgart

 

Other publications of authors with the same name

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays., , , , , , and . AHS, page 1-8. IEEE, (2015)Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing., , , and . PARCO, volume 25 of Advances in Parallel Computing, page 53-62. IOS Press, (2013)On-demand fault-tolerant loop processing on massively parallel processor arrays., , , , and . ASAP, page 194-201. IEEE Computer Society, (2015)Distributed Resource Reservation in Massively Parallel Processor Arrays., , and . IPDPS Workshops, page 318-321. IEEE, (2011)Hierarchical power management for adaptive tightly-coupled processor arrays., , , , , and . ACM Trans. Design Autom. Electr. Syst., 18 (1): 2:1-2:25 (2012)Massively Parallel Processor Architectures for Resource-aware Computing., , , and . CoRR, (2014)Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms., , , , and . ACSSC, page 398-403. IEEE, (2014)Self-adaptive harris corner detector on heterogeneous many-core processor., , , , , , , and . DASIP, page 1-8. IEEE, (2014)Techniques for on-demand structural redundancy for massively parallel processor arrays., , , , , and . Journal of Systems Architecture - Embedded Systems Design, 61 (10): 615-627 (2015)System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance., , and . ICPP Workshops, page 528-534. IEEE Computer Society, (2009)