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Disambiguation of "Teich, Jürgen"

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System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance.

, , and . ICPP Workshops, page 528-534. IEEE Computer Society, (2009)

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apl. Prof. Dr. Jürgen Pleiss University of Stuttgart

Univ. -Prof. Dr. Jürgen Pafel University of Stuttgart

Dr. rer. nat. Jürgen Steinwandel University of Stuttgart

Hon. -Prof. Dr. Jürgen Hammer University of Stuttgart

Hon. -Prof. Dr. Jürgen Blum University of Stuttgart

 

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Online placement for dynamically reconfigurable devices., , and . IJES, 1 (3/4): 165-178 (2005)An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)., , and . FPGA, page 257. ACM, (2014)Buffer Memory Optimization in DSP Applications - An Evolutionary Approach., , and . PPSN, volume 1498 of Lecture Notes in Computer Science, page 885-896. Springer, (1998)Auto-vectorization for image processing DSLs., , , and . LCTES, page 21-30. ACM, (2017)Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor., , , and . MARC Symposium, page 111-114. KIT Scientific Publishing, Karlsruhe, (2011)HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN)., , and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 159-170. Springer, (2013)On Confident Task-Accurate Performance Estimation., , , , and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 25-37. Springer, (2013)06141 Abstracts Collection -- Dynamically Reconfigurable Architectures., , , and . Dynamically Reconfigurable Architectures, volume 06141 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2006)06141 Executive Summary -- Dynamically Reconfigurable Architectures., , , and . Dynamically Reconfigurable Architectures, volume 06141 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2006)New Directions for IP Core Watermarking and Identification., and . Dynamically Reconfigurable Architectures, volume 10281 of Dagstuhl Seminar Proceedings, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany, (2010)