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Techniques for on-demand structural redundancy for massively parallel processor arrays.

V. Lari, J. Teich, A. Tanase, M. Witterauf, F. Khosravi, and B. Meyer. Journal of Systems Architecture - Embedded Systems Design, 61 (10): 615-627 (2015)

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Dr. Michael Zwick University of Stuttgart

Wahrnehmung von Technik und Digitalisierung in Deutschland und Europa : Befunde aus dem TechnikRadarC. Störk-Biber, J. Hampel, C. §4Kropp, and M. Zwick. HMD - Praxis der Wirtschaftsinformatik, 57 (1): 21-32 (2020)

Apl. Prof. Dr. -Ing. Michael Seidenfuß University of Stuttgart

Univ. -Prof. Dr. -Ing. Michael Schmidt University of Stuttgart

Prof. (Ord) Dr. Michael Mehring University of Stuttgart

PD Dr. Michael Schanz University of Stuttgart

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Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays.C. Heidorn, M. Witterauf, F. Hannig, and J. Teich. JCP, 14 (8): 541-556 (2019)Techniques for on-demand structural redundancy for massively parallel processor arrays.V. Lari, J. Teich, A. Tanase, M. Witterauf, F. Khosravi, and B. Meyer. Journal of Systems Architecture - Embedded Systems Design, 61 (10): 615-627 (2015)Anytime instructions for programmable accuracy floating-point arithmetic.M. Brand, M. Witterauf, F. Hannig, and J. Teich. CF, page 215-219. ACM, (2019)On-demand fault-tolerant loop processing on massively parallel processor arrays.A. Tanase, M. Witterauf, J. Teich, F. Hannig, and V. Lari. ASAP, page 194-201. IEEE Computer Society, (2015)A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.V. Lari, A. Tanase, J. Teich, M. Witterauf, F. Khosravi, F. Hannig, and B. Meyer. AHS, page 1-8. IEEE, (2015)Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.É. Sousa, M. Witterauf, M. Brand, A. Tanase, F. Hannig, and J. Teich. ASAP, page 1-9. IEEE Computer Society, (2018)Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates.M. Witterauf, F. Hannig, and J. Teich. RSP, page 9-15. ACM, (2017)Adaptive fault tolerance through invasive computing.M. Witterauf, A. Tanase, J. Teich, V. Lari, A. Zwinkau, and G. Snelting. AHS, page 1-8. IEEE, (2015)Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays.A. Tanase, M. Witterauf, J. Teich, and F. Hannig. MEMOCODE, page 188-197. IEEE, (2015)Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays.A. Tanase, M. Witterauf, J. Teich, and F. Hannig. ACM Trans. Embedded Comput. Syst., 17 (2): 31:1-31:27 (2018)