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Disambiguation of "Sousa, Éricles Rodrigues"

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Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.

, , , , , and . ASAP, page 1-9. IEEE Computer Society, (2018)

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Nils Rodrigues University of Stuttgart

A Visual Analytics Approach for Word Relevances in Multiple Texts, , , and . (2017)

Prof. Dr. Alfonso Sousa-Poza University of Stuttgart

Aimee Sousa Calepso University of Stuttgart

Dr. Preston Francisco Rodrigues University of Stuttgart

Franklin Luis Dos Santos Rodrigues Junior University of Stuttgart

 

Other publications of authors with the same name

A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays., , , and . ReConFig, page 1-8. IEEE, (2017)Dark silicon management: an integrated and coordinated cross-layer approach., , , , , , , , , and 6 other author(s). it - Information Technology, 58 (6): 297-307 (2016)Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays., , , and . DASIP, page 88-95. IEEE, (2013)Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study., , , , , and . ASAP, page 1-9. IEEE Computer Society, (2018)TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays., , , , and . ReConFig, page 1-3. IEEE, (2017)Resource-awareness on heterogeneous MPSoCs for image processing., , , , , , , , , and 6 other author(s). Journal of Systems Architecture - Embedded Systems Design, 61 (10): 668-680 (2015)Power Density-Aware Resource Management for Heterogeneous Tiled Multicores., , , , , , , , and . IEEE Trans. Computers, 66 (3): 488-501 (2017)Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures., , , and . DSD, page 74-81. IEEE Computer Society, (2014)A prototype of an adaptive computer vision algorithm on MPSoC architecture., , , and . DASIP, page 353-354. IEEE, (2013)Memory and interface architectures for invasive tightly coupled processor arrays = Speicher- und Schnittstellenarchitekturen für invasive eng gekoppelte Prozessorfelder.. University of Erlangen-Nuremberg, Germany, (2018)