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Design of an integrated potentiostat circuit for CMOS bio sensor chips., , , , , , , , , and 3 other author(s). ISCAS (5), page 9-12. IEEE, (2003)A Robust Synchronized 2N2P LC Oscillator with a Shut-down Mode for Adiabatic Logic Circuits., , and . ISCAS, page 241-244. IEEE, (2009)In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations., , , , and . J. Solid-State Circuits, 42 (7): 1583-1592 (2007)A 13.56MHz class e power amplifier for inductively coupled DC supply with 95% power added efficiency (PAE)., , , , and . EURFID, page 87-93. IEEE, (2015)Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A., , , , , and . ESSDERC, page 97-100. IEEE, (2015)Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 392-401. Springer, (2004)A Design Space Comparison of 6T and 8T SRAM Core-Cells., , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 116-125. Springer, (2008)Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization., , , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 126-135. Springer, (2008)Energieoptimierung durch Adiabatische Schaltungstechnik., , , and . GI Jahrestagung (1), volume P-67 of LNI, page 446. GI, (2005)A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters., , and . ICCAD, page 554-561. IEEE Computer Society / ACM, (1995)