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Disambiguation of "Reis, Ricardo"

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Using TSVs for thermal mitigation in 3D circuits: Wish and truth.

, , , , , , , , , , and . 3DIC, page 1-8. IEEE, (2014)

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Dr. Pascal Fabian Reisert University of Stuttgart

Dr. Ellen Reister University of Stuttgart

Rodolfo Reis Soldati University of Stuttgart

Dr. -Ing. Martin Reiser University of Stuttgart

Stefanie Reisinger University of Stuttgart

 

Other publications of authors with the same name

Design of a Robust 8-Bit Microprocessor to Soft Errors., , and . IOLTS, page 195-196. IEEE Computer Society, (2006)Statistical and Numerical Approach for a Computer efficient circuit yield analysis., , , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-24. Springer, (2007)An Educational Tool for Design Automation of CMOS Cells., , and . MSE, page 149-150. IEEE Computer Society, (2007)A CAL Tool to Aid the Understanding of Logic Synthesis., , and . MSE, page 49-50. IEEE Computer Society, (2007)Design of Very Deep Pipelined Multipliers for FPGAs., , , , , and . DATE, page 52-57. IEEE Computer Society, (2004)Exploiting memory allocations in clusterised many-core architectures., , , , , and . IET Computers & Digital Techniques, 13 (4): 302-311 (2019)Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing., , , and . SBCCI, page 220-225. ACM, (2006)Process and temperature impact on single-event transients in 28nm FDSOI CMOS., , and . LASCAS, page 1-4. IEEE, (2017)gem5-FIM: a flexible and scalable multicore soft error assessment framework to early reliability design space explorations., , and . LASCAS, page 1-4. IEEE, (2018)Reducing the amount of transistors by gate merging., , and . LASCAS, page 1-4. IEEE, (2018)