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Design of a Robust 8-Bit Microprocessor to Soft Errors.

, , and . IOLTS, page 195-196. IEEE Computer Society, (2006)

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Logic and Physical Synthesis of Cell Arrays., , and . ICECS, page 1292-1295. IEEE, (2007)An Educational Tool for Design Automation of CMOS Cells., , and . MSE, page 149-150. IEEE Computer Society, (2007)A CAL Tool to Aid the Understanding of Logic Synthesis., , and . MSE, page 49-50. IEEE Computer Society, (2007)Design of a Robust 8-Bit Microprocessor to Soft Errors., , and . IOLTS, page 195-196. IEEE Computer Society, (2006)Design of Very Deep Pipelined Multipliers for FPGAs., , , , , and . DATE, page 52-57. IEEE Computer Society, (2004)Exploiting memory allocations in clusterised many-core architectures., , , , , and . IET Computers & Digital Techniques, 13 (4): 302-311 (2019)A New Nonlinear Global Placement for FPGAs: The Chaotic Place., , and . IEEE Trans. on Circuits and Systems, 66-I (6): 2165-2174 (2019)Path planning aware of soil compaction for steep slope vineyards., , , , , , and . ICARSC, page 250-255. IEEE, (2018)System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit., , , , , and . 3DIC, page 1-6. IEEE, (2013)Design Tools and Methods for Chip Physical Design.. Multiprocessor System-on-Chip, Springer, (2011)