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An Educational Tool for Design Automation of CMOS Cells.

, , and . MSE, page 149-150. IEEE Computer Society, (2007)

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An Educational Tool for Design Automation of CMOS Cells., , and . MSE, page 149-150. IEEE Computer Society, (2007)Efficient shift-adds design of digit-serial multiple constant multiplications., , , , and . ACM Great Lakes Symposium on VLSI, page 61-66. ACM, (2011)An automated design methodology for layout generation targeting power leakage minimization., , and . ICECS, page 81-84. IEEE, (2009)Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study., , and . IOLTS, page 165-172. IEEE Computer Society, (2006)Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 498-511 (2013)Optimization of area in digit-serial Multiple Constant Multiplications at gate-level., , , , and . ISCAS, page 2737-2740. IEEE, (2011)Voltage-mode quaternary FPGAs: An evaluation of interconnections., , , and . ISCAS, page 869-872. IEEE, (2010)An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs., , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 84-93. Springer, (2010)A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming., , and . VLSI-SoC, volume 240 of IFIP, page 331-344. Springer, (2005)A Transistor Sizing Method Applied to an Automatic Layout Generation Tool., , , , and . SBCCI, page 303-. IEEE Computer Society, (2003)