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On the feasibility of combining on-line-test and self repair for logic circuits.

T. Koal, M. Ulbricht, P. Engelke, and H. Vierhaus. DDECS, page 187-192. IEEE Computer Society, (2013)

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Patrick Pietrantuono University of Stuttgart

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Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.I. Polian, S. Kundu, J. Gallière, P. Engelke, M. Renovell, and B. Becker. VTS, page 343-348. IEEE Computer Society, (2005)SUPERB: Simulator utilizing parallel evaluation of resistive bridges.P. Engelke, B. Becker, M. Renovell, J. Schlöffel, B. Braitling, and I. Polian. ACM Trans. Design Autom. Electr. Syst., 14 (4): 56:1-56:21 (2009)Simulating Resistive-Bridging and Stuck-At Faults.P. Engelke, I. Polian, M. Renovell, and B. Becker. IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (10): 2181-2192 (2006)TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, and B. Becker. VLSI Design, page 227-232. IEEE Computer Society, (2009)X-Masking During Logic BIST and Its Impact on Defect Coverage.Y. Tang, H. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker. ITC, page 442-451. IEEE Computer Society, (2004)A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, and B. Becker. European Test Symposium, page 113-118. IEEE Computer Society, (2008)An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.N. Houarche, M. Comte, M. Renovell, A. Czutro, P. Engelke, I. Polian, and B. Becker. VTS, page 21-26. IEEE Computer Society, (2009)The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.P. Engelke, I. Polian, M. Renovell, B. Seshadri, and B. Becker. VTS, page 171-178. IEEE Computer Society, (2004)Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.I. Polian, P. Engelke, and B. Becker. ISMVL, page 216-223. IEEE Computer Society, (2002)Resistive Bridging Fault Simulation of Industrial Circuits.P. Engelke, I. Polian, J. Schlöffel, and B. Becker. DATE, page 628-633. ACM, (2008)

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Disambiguation of "Engelke, Piet"

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On the feasibility of combining on-line-test and self repair for logic circuits.

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Patrick Pietrantuono University of Stuttgart

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Disambiguation of "Engelke, Piet"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML On the feasibility of combining on-line-test and self repair for logic circuits.

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Patrick Pietrantuono University of Stuttgart

Other publications of authors with the same name

Disambiguation

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On the feasibility of combining on-line-test and self repair for logic circuits.