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Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding.

, , and . IEEE Trans. VLSI Syst., 22 (7): 1515-1525 (2014)

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Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis., , , , and . DATE, page 801-806. IEEE, (2010)Decoder Hardware Architecture for HEVC., , , , and . High Efficiency Video Coding, Springer, (2014)A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications., , , , and . J. Solid-State Circuits, 49 (1): 61-72 (2014)HEVC interpolation filter architecture for quad full HD decoding., , , and . VCIP, page 1-5. IEEE, (2013)A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices., , and . J. Solid-State Circuits, 53 (8): 2368-2377 (2018)Technique for Efficient Evaluation of SRAM Timing Failure., , , , and . IEEE Trans. VLSI Syst., 21 (8): 1558-1562 (2013)An energy-scalable accelerator for blind image deblurring., , and . ESSCIRC, page 113-116. IEEE, (2016)A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications., , , , and . ISSCC, page 162-163. IEEE, (2013)Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding., , and . IEEE Trans. VLSI Syst., 22 (7): 1515-1525 (2014)Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization., , , and . ICIP, page 2100-2104. IEEE, (2014)