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Disambiguation of "Qazi, Masood"

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Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis.

, , , , and . DATE, page 801-806. IEEE, (2010)

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Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems., , , , , and . IEEE Trans. on Circuits and Systems, 59-II (9): 533-537 (2012)40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS., , , and . DATE, page 1637-1642. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis., , , , and . DATE, page 801-806. IEEE, (2010)A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$m$ CMOS for Nonvolatile Processing in Digital Systems., , and . J. Solid-State Circuits, 49 (1): 202-211 (2014)A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems., , and . ISSCC, page 192-193. IEEE, (2013)Technique for Efficient Evaluation of SRAM Timing Failure., , , , and . IEEE Trans. VLSI Syst., 21 (8): 1558-1562 (2013)A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS., , , and . J. Solid-State Circuits, 46 (1): 85-96 (2011)A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS., , , and . ISSCC, page 208-210. IEEE, (2011)A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS., , , and . ISSCC, page 350-351. IEEE, (2010)Challenges and Directions for Low-Voltage SRAM., , and . IEEE Design & Test of Computers, 28 (1): 32-43 (2011)