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Disambiguation of "Huang, Chao-Tsung"

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Decoder Hardware Architecture for HEVC.

, , , , and . High Efficiency Video Coding, Springer, (2014)

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Zhenxiang Huang University of Stuttgart

Jingjing Huang University of Stuttgart

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Dr. -Ing. Min Huang University of Stuttgart

Shih-Min Huang University of Stuttgart

 

Other publications of authors with the same name

Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank., , and . ICIP (2), page 571-574. (2003)VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization., , and . VLSI Signal Processing, 40 (3): 343-353 (2005)Fast realistic refocusing for sparse light fields., , , , and . ICASSP, page 1176-1180. IEEE, (2015)B-spline factorization-based architecture for inverse discrete wavelet transform., , and . ISCAS (2), page 829-832. IEEE, (2004)Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC., , , , and . ISCAS (2), page 1790-1793. IEEE, (2005)Decoder Hardware Architecture for HEVC., , , , and . High Efficiency Video Coding, Springer, (2014)Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization., , , and . ICIP, page 2100-2104. IEEE, (2014)Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method., , and . APCCAS (1), page 363-366. IEEE, (2002)Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding., , and . IEEE Trans. VLSI Syst., 22 (7): 1515-1525 (2014)A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications., , , , and . ISSCC, page 162-163. IEEE, (2013)