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Disambiguation of "Schlichtmann, Ulf"

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ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.

, , , , , and . DATE, page 609-612. IEEE, (2018)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

apl. Prof. Dr. -Ing. Ulf Nürnberger University of Stuttgart

Hon. -Prof. Dr. Ulf Plöcker University of Stuttgart

Ulf Bischoff University of Stuttgart

Hon. -Prof. Dr. Ulf Häusler University of Stuttgart

 

Other publications of authors with the same name

Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs., , , , , , , and . DATE, page 538. IEEE Computer Society, (2002)The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (12): 2209-2222 (2008)Goal oriented slicing enumeration through shape function clipping., and . EURO-DAC, page 361-365. EEE Computer Society, (1991)Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance.. DSD, page 52-59. IEEE Computer Society, (2004)Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices., , , and . Microelectronics Journal, (2018)PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer., , , and . JETC, 12 (4): 44:1-44:28 (2016)EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (4): 705-718 (2019)Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (12): 1981-1994 (2016)Machine learning and structural characteristics for reverse engineering., , , and . ASP-DAC, page 96-103. ACM, (2019)On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions., , , , , , , and . IACR Cryptology ePrint Archive, (2009)