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EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.

, , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (4): 705-718 (2019)

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EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (4): 705-718 (2019)Application of machine learning methods in post-silicon yield improvement., , , , and . SoCC, page 243-248. IEEE, (2017)Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units., , , and . DAC, page 26:1-26:6. ACM, (2018)EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers., , and . DAC, page 60:1-60:6. ACM, (2016)Sampling-based buffer insertion for post-silicon yield improvement under process variability., , and . DATE, page 1457-1460. IEEE, (2016)EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers., , and . CoRR, (2017)Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability., , and . CoRR, (2017)PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model., , and . ICCAD, page 100. ACM, (2016)Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing., , , , and . DATE, page 1751-1756. IEEE, (2019)PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model., , and . CoRR, (2017)