%0 Journal Article %1 journals/tcad/Zhang0SHS19 %A Zhang, Grace Li %A Li, Bing %A Shi, Yiyu %A Hu, Jiang %A Schlichtmann, Ulf %D 2019 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 4 %P 705-718 %T EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. %U http://dblp.uni-trier.de/db/journals/tcad/tcad38.html#Zhang0SHS19 %V 38

@article{journals/tcad/Zhang0SHS19, added-at = {2019-04-12T00:00:00.000+0200}, author = {Zhang, Grace Li and Li, Bing and Shi, Yiyu and Hu, Jiang and Schlichtmann, Ulf}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2a8f91f55d7d7c2fb58b9a12ae21ac53f/dblp}, ee = {https://doi.org/10.1109/TCAD.2018.2818713}, interhash = {590479b407cc540b312a5820ae1f1e5c}, intrahash = {a8f91f55d7d7c2fb58b9a12ae21ac53f}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 4, pages = {705-718}, timestamp = {2019-09-27T08:26:52.000+0200}, title = {EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad38.html#Zhang0SHS19}, volume = 38, year = 2019 }