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Disambiguation of "Graeb, Helmut E."

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The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (12): 2209-2222 (2008)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hon. -Prof. Dr. -Ing. Helmut Lotz University of Stuttgart

Prof. Dr. Helmut Bertagnolli University of Stuttgart

E. Garrelts

Dr. Helmut Haas University of Stuttgart

Frederic Graeb University of Stuttgart

 

Other publications of authors with the same name

Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults., , and . DATE, page 822-827. IEEE Computer Society, (1998)Automatic generation of hierarchical placement rules for analog integrated circuits., , , and . ISPD, page 47-54. ACM, (2010)The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits., , , and . DATE, page 42-47. IEEE Computer Society / ACM, (2000)Design based analog testing by Characteristic Observation Inference., , and . ICCAD, page 620-626. IEEE Computer Society / ACM, (1995)Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (10): 1733-1748 (2007)Performance trade-off analysis of analog circuits by normal-boundary intersection., , and . DAC, page 958-963. ACM, (2003)Deterministic approaches to analog performance space exploration (PSE)., , , and . DAC, page 869-874. ACM, (2005)Fast evaluation of analog circuit structures by polytopal approximations., , , and . ISCAS, IEEE, (2006)Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen., , , and . GI Jahrestagung (1), volume P-67 of LNI, page 334-338. GI, (2005)DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (8): 1229-1242 (2016)