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PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer.

, , , and . JETC, 12 (4): 44:1-44:28 (2016)

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Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems., , and . INA-OCMC@HiPEAC, page 5-8. IEEE Computer Society, (2015)A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip., , , , and . ACM Great Lakes Symposium on VLSI, page 267-272. ACM, (2014)Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints., , and . NOCS, page 185-192. IEEE Computer Society, (2012)Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems., , , , and . AISTECS@HiPEAC, page 3:1-3:6. ACM, (2016)A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings., , , and . ASP-DAC, page 300-305. IEEE, (2017)Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain., , , , , , , , and . NOCS, page 72-79. IEEE, (2014)Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors., and . NoCArc@MICRO, page 25-30. ACM, (2012)Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System., , , , and . IEEE Trans. VLSI Syst., 25 (7): 2081-2094 (2017)PROTON: an automatic place-and-route tool for optical networks-on-chip., , , and . ICCAD, page 138-145. IEEE, (2013)