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A Hardware-Software System for Tomographic Reconstruction.

, , , and . Journal of Circuits, Systems, and Computers, 12 (2): 203- (2003)

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Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing., , and . IEEE Congress on Evolutionary Computation, page 1-8. IEEE, (2012)Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel., , and . VLSI Design, page 104-109. IEEE Computer Society, (2000)Massively Parallel Processor Architectures: A Co-design Approach., , , , , , , , and . ReCoSoC, page 61-68. Univ. Montpellier II, (2007)A Hardware-Software System for Tomographic Reconstruction., , , and . Journal of Circuits, Systems, and Computers, 12 (2): 203- (2003)Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism., , , and . DSD, page 391-398. IEEE Computer Society, (2008)Causality Constraints for Processor Architectures with Sub-Word Parallelism., , and . DSD, page 82-89. IEEE Computer Society, (2003)Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels., , and . PARELEC, page 173-180. IEEE Computer Society, (2006)Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)Derivation of Packing Instructions for Exploiting Sub-Word Parallelism., , and . PARELEC, page 167-172. IEEE Computer Society, (2006)Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)