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Disambiguation of "Kupriyanov, Alexey"

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Co-Design of Massively Parallel Embedded Processor Architectures.

, , , , , , , , , , , and . ReCoSoC, page 27-34. Univ. Montpellier II, (2005)

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Dr. Alexey Lapin University of Stuttgart

 

Other publications of authors with the same name

Efficient event-driven simulation of parallel processor architectures., , , and . SCOPES, volume 235 of ACM International Conference Proceeding Series, page 71-80. (2007)A Generic Framework for Rapid Prototyping of System-on-Chip Designs., , , , and . CDES, page 189-195. CSREA Press, (2006)Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)Modeling of Interconnection Networks in Massively Parallel Processor Architectures., , , , , , and . ARCS, volume 4415 of Lecture Notes in Computer Science, page 268-282. Springer, (2007)Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)A highly parameterizable parallel processor array architecture., , , and . FPT, page 105-112. IEEE, (2006)Massively Parallel Processor Architectures: A Co-design Approach., , , , , , , , and . ReCoSoC, page 61-68. Univ. Montpellier II, (2007)High-Speed Event-Driven RTL Compiled Simulation., , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 519-529. Springer, (2004)A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template., , , and . ReCoSoC, page 31-37. Univ. Montpellier II, (2006)An Architecture Description Language for Massively Parallel Processor Architectures., , , , , and . MBMV, page 11-20. Fraunhofer Institut für Integrierte Schaltungen, (2006)