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Disambiguation of "Chillet, Daniel"

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Co-Design of Massively Parallel Embedded Processor Architectures.

, , , , , , , , , , , and . ReCoSoC, page 27-34. Univ. Montpellier II, (2005)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. rer. nat. Daniel Hernandez University of Stuttgart

An Ontology for the Reuse and Tracking of Prefabricated Building Components, , , , , and . Proceedings of the The 2nd International Workshop on Knowledge Graphs for Sustainability (KG4S 2024) colocated with the 21st Extended Semantic Web Conference (ESWC 2024), 3753, page 53-64. CEUR, (May 2024)
An Ontology for the Reuse and Tracking of Prefabricated Building Components, , , , , and . Proceedings of the The 2nd International Workshop on Knowledge Graphs for Sustainability (KG4S 2024) colocated with the 21st Extended Semantic Web Conference (ESWC 2024), 3753, page 53-64. CEUR, (May 2024)Proceedings of the The 2nd International Workshop on Knowledge Graphs for Sustainability (KG4S 2024) colocated with the 21st Extended Semantic Web Conference (ESWC 2024), , , , , and (Eds.) 3753, CEUR, (May 2024)

Daniel Widmann University of Stuttgart

A SiGe-HBT 2:1 analog multiplexer with more than 67 GHz bandwidth, , , , , , , , , and . 2017 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), page 146-149. 978-1-5090-6383-3 and 978-1-5090-6382-6 and 978-1-5090-6384-0, IEEE, (2017)

Apl. Prof. Dr. -Ing. Daniel Dobslaw University of Stuttgart

Daniel Gutsche University of Stuttgart

Daniel Tandler University of Stuttgart

 

Other publications of authors with the same name

VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters., , , and . ICASSP, page 671-674. IEEE Computer Society, (1997)DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints., , , and . IPDPS, IEEE Computer Society, (2002)Memory aspects in signal processing and HLS tool: Some results., , , and . EUSIPCO, page 1-4. IEEE, (1996)Asynchronous timing model for high-level synthesis of DSP applications., , and . EUSIPCO, page 1-4. IEEE, (1998)Power consumption model for partial and dynamic reconfiguration., , , and . ReConFig, page 1-8. IEEE, (2012)A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 51-62. Kluwer, (2001)Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures., , , , and . Int. J. Reconfig. Comp., (2010)Parallelism Level Impact on Energy Consumption in Reconfigurable Devices., , , and . SIGARCH Computer Architecture News, 39 (4): 104-105 (2011)Approximate nanophotonic interconnects., , , and . NOCS, page 9:1-9:7. ACM, (2019)Power consumption models for the use of dynamic and partial reconfiguration., , , and . Microprocessors and Microsystems - Embedded Hardware Design, 38 (8): 860-872 (2014)