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Disambiguation of "Merker, Renate"

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Co-Design of Massively Parallel Embedded Processor Architectures.

, , , , , , , , , , , and . ReCoSoC, page 27-34. Univ. Montpellier II, (2005)

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apl. Prof. Dr. Renate Breuninger University of Stuttgart

Univ. -Prof. Dr. Renate Brosch University of Stuttgart

Dr. Renate Zapf-Gottwick University of Stuttgart

 

Other publications of authors with the same name

Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)Derivation of Packing Instructions for Exploiting Sub-Word Parallelism., , and . PARELEC, page 167-172. IEEE Computer Society, (2006)Hierarchical algorithm partitioning at system level for an improved utilization of memory structures., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (1): 14-24 (1999)An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs., , , , and . FPL, page 92-98. IEEE, (2009)Optimization of the Background Memory Utilization by Partitioning., and . ISSS, page 82-89. ACM / IEEE Computer Society, (1997)A Cost Model for Partial Dynamic Reconfiguration., and . Trans. HiPEAC, (2011)Optimized Data-Reuse in Processor Arrays., and . ASAP, page 315-325. IEEE Computer Society, (2004)Determination of the Processor Functionality in the Design of Processor Arrays., and . ASAP, page 199-208. IEEE Computer Society, (1997)Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)Synthesis of efficiently reconfigurable datapaths for reconfigurable computing., and . FPT, page 277-280. IEEE, (2008)