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Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)Optimized Data-Reuse in Processor Arrays., and . ASAP, page 315-325. IEEE Computer Society, (2004)Co-Design of Massively Parallel Embedded Processor Architectures., , , , , , , , , and 2 other author(s). ReCoSoC, page 27-34. Univ. Montpellier II, (2005)Massively Parallel Processor Architectures: A Co-design Approach., , , , , , , , and . ReCoSoC, page 61-68. Univ. Montpellier II, (2007)A Parallel Hardware-Software System for Signal Processing Algorithms., , , , , and . PARELEC, page 215-220. IEEE Computer Society, (2004)Abbildungsverfahren zur effizienten Implementierung rechenintensiver Algorithmen auf Prozessorarrays.. Dresden University of Technology, (2010)Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints., and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 1181-1191. Springer, (2006)Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy., and . ASAP, page 28-32. IEEE Computer Society, (2006)Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels., , and . PARELEC, page 173-180. IEEE Computer Society, (2006)Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching., , and . IPDPS, IEEE Computer Society, (2005)