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Co-Design of Massively Parallel Embedded Processor Architectures.

F. Hannig, H. Dutta, A. Kupriyanov, J. Teich, R. Schaffer, S. Siegel, R. Merker, R. Keryell, B. Pottier, D. Chillet, D. Menard, and O. Sentieys. ReCoSoC, page 27-34. Univ. Montpellier II, (2005)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Daniel Holder University of Stuttgart

Laser micromachining of bionic transport structures on cemented tungsten carbide for passive directional transport of lubricantsD. Holder, N. Kessenbrock, K. Cirakoglu, C. Hagenlocher, and T. Graf. 123, page 452–457. Elsevier BV, (2024)

Dr. -Ing. Daniel Markthaler University of Stuttgart

Replication Data for: Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesisN. Hansen, and D. Markthaler. Dataset, (2024)Related to: Schneider, Andreas; Lystbæk, Thomas B.; Markthaler, Daniel; Hansen, Niels; Hauer, Bernhard (2024): Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis. In: Nature Communications, 15, 4925. doi: 10.1038/s41467-024-48993-9.

Univ. -Prof. Dr. Daniel Weiskopf University of Stuttgart

Supplemental Materials for: Visual Analysis of Fitness Landscapes in Architectural Design OptimizationM. Abdelaal, M. Galuschka, M. Zorn, F. Kannenberg, A. Menges, T. Wortmann, D. Weiskopf, and K. Kurzhals. Software, (2024)Related to: Manuscript accepted for publication in the Visual Computer journal.

Daniel Marino

Daniel Roth

Other publications of authors with the same name

Power consumption model for partial and dynamic reconfiguration.R. Bonamy, D. Chillet, S. Bilavarn, and O. Sentieys. ReConFig, page 1-8. IEEE, (2012)A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.R. David, D. Chillet, S. Pillement, and O. Sentieys. VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 51-62. Kluwer, (2001)VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters.J. Diguet, O. Sentieys, D. Chillet, and J. Philippe. ICASSP, page 671-674. IEEE Computer Society, (1997)DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.R. David, D. Chillet, S. Pillement, and O. Sentieys. IPDPS, IEEE Computer Society, (2002)Asynchronous timing model for high-level synthesis of DSP applications.J. Dedou, D. Chillet, and O. Sentieys. EUSIPCO, page 1-4. IEEE, (1998)Memory aspects in signal processing and HLS tool: Some results.J. Philippe, D. Chillet, O. Sentieys, and J. Diguet. EUSIPCO, page 1-4. IEEE, (1996)Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures.L. Devaux, S. Sassi, S. Pillement, D. Chillet, and D. Demigny. Int. J. Reconfig. Comp., (2010)Parallelism Level Impact on Energy Consumption in Reconfigurable Devices.R. Bonamy, D. Chillet, O. Sentieys, and S. Bilavarn. SIGARCH Computer Architecture News, 39 (4): 104-105 (2011)Approximate nanophotonic interconnects.J. Lee, C. Killian, S. Beux, and D. Chillet. NOCS, page 9:1-9:7. ACM, (2019)Power consumption models for the use of dynamic and partial reconfiguration.R. Bonamy, S. Bilavarn, D. Chillet, and O. Sentieys. Microprocessors and Microsystems - Embedded Hardware Design, 38 (8): 860-872 (2014)