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Disambiguation of "Lee, Kuen-Di"

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A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.

, , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (5): 958-962 (2015)

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Moosung Lee University of Stuttgart

Dongwon Lee University of Stuttgart

Junghwa Lee University of Stuttgart

Di Liu University of Stuttgart

Ph. D. Benjamin Lee University of Stuttgart

 

Other publications of authors with the same name

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist., , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (5): 958-962 (2015)A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist., , , , , , , , , and 9 other author(s). ISCAS, page 1468-1471. IEEE, (2013)A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 59-II (12): 863-867 (2012)High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder., , , , , , , , , and 6 other author(s). ISCAS, page 1831-1834. IEEE, (2012)Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array., , , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array., , , , , , , , , and 1 other author(s). VLSI-DAT, page 1-4. IEEE, (2012)A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 64-I (7): 1791-1802 (2017)A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist., , , , , , , , , and 3 other author(s). SoCC, page 218-223. IEEE, (2012)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , and . Microelectronics Journal, (2016)