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Disambiguation of "Tu, Ming-Hsien"

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A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.

, , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (5): 958-962 (2015)

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Kilian Türk University of Stuttgart

Gregory-Jamie Tüzün University of Stuttgart

Gregory-Jamie Tüzün

Fabrizio Turco University of Stuttgart

Dr. phil. Rostislav Tumanov University of Stuttgart

 

Other publications of authors with the same name

Testing strategies for a 9T sub-threshold SRAM., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , and . Microelectronics Journal, (2016)Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist., , , , and . IEEE Trans. on Circuits and Systems, 57-I (12): 3039-3047 (2010)40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist., , , , , , and . IEEE Trans. on Circuits and Systems, 61-I (9): 2578-2585 (2014)A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist., , , , , and . ISLPED, page 51-56. IEEE, (2013)A reconfigurable MAC architecture implemented with mixed-Vt standard cell library., , , , , and . ISCAS, page 3426-3429. IEEE, (2008)A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 59-II (12): 863-867 (2012)Asymmetrical Write-assist for single-ended SRAM operation., , , , and . SoCC, page 101-104. IEEE, (2009)Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array., , , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 64-I (7): 1791-1802 (2017)