PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Huang, Huan-Shun"

Author of the publication

copydeleteadd this publication to your clipboard
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.

, , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (5): 958-962 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Zhenxiang Huang University of Stuttgart

Jingjing Huang University of Stuttgart

Shih-Min Huang University of Stuttgart

Dr. -Ing. Min Huang University of Stuttgart

 

Other publications of authors with the same name

A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 59-II (12): 863-867 (2012)A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 64-I (7): 1791-1802 (2017)A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist., , , , , , , , , and . IEEE Trans. VLSI Syst., 23 (5): 958-962 (2015)A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist., , , , , , , , , and 9 other author(s). ISCAS, page 1468-1471. IEEE, (2013)A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control., , , , , , , , , and 3 other author(s). SoCC, page 110-115. IEEE, (2013)A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists., , , , , , , , , and 2 other author(s). SoCC, page 455-462. IEEE, (2014)A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 47 (6): 1469-1482 (2012)A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist., , , , , , , , and . ISLPED, page 79-84. ACM, (2012)A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , and . Microelectronics Journal, (2016)