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A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)Histogram analysis of T2*-based pharmacokinetic imaging in cerebral glioma grading., , , , , , , , and . Computer Methods and Programs in Biomedicine, (2018)Design of 2.45GHz Planar Meander Dipole Antenna., , , and . IIH-MSP, page 5-8. IEEE Computer Society, (2011)A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist., , , , , , , , , and 9 other author(s). ISCAS, page 1468-1471. IEEE, (2013)An all-digital bit transistor characterization scheme for CMOS 6T SRAM array., , , , , , , , , and . ISCAS, page 2485-2488. IEEE, (2012)Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM., , , , , , , , , and 1 other author(s). APCCAS, page 116-119. IEEE, (2012)A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 47 (6): 1469-1482 (2012)High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder., , , , , , , , , and 6 other author(s). ISCAS, page 1831-1834. IEEE, (2012)Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array., , , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array., , , , , , , , , and 1 other author(s). VLSI-DAT, page 1-4. IEEE, (2012)