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Disambiguation of "Ostúa, Enrique"

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Design of a FFT/IFFT module as an IP core suitable for embedded systems.

, , , , , , , and . SIES, page 337-340. IEEE, (2007)

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Dr. -Ing. Nelson Enrique Bances Purizaca University of Stuttgart

 

Other publications of authors with the same name

Improving the Performance of Static CMOS Gates by Using Independent Bodies., , , , , , and . J. Low Power Electronics, 3 (1): 70-77 (2007)Internode: Internal Node Logic Computational Model., , , , , and . Annual Simulation Symposium, page 241-248. IEEE Computer Society, (2003)Signal Sampling Based Transition Modeling for Digital Gates Characterization., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 829-837. Springer, (2004)Static Power Consumption in CMOS Gates Using Independent Bodies., , , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)Minimalistic SDHC-SPI hardware reader module for boot loader applications., , , , , and . Microelectronics Journal, (2017)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , and . IES, page 1-7. IEEE, (2006)Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates., , , , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 337-347. Springer, (2005)Logic-Level Fast Current Simulation for Digital CMOS Circuits., , , , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 425-435. Springer, (2005)Design of a FFT/IFFT module as an IP core suitable for embedded systems., , , , , , , and . SIES, page 337-340. IEEE, (2007)Accurate Logic-Level Current Estimation for Digital CMOS Circuits., , , , , , and . J. Low Power Electronics, 2 (1): 87-94 (2006)