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Design of a FFT/IFFT module as an IP core suitable for embedded systems.

J. Viejo, A. Millán, M. Bellido, J. Juan, P. de Clavijo, D. Guerrero, E. Ostúa, and A. Muñoz. SIES, page 337-340. IEEE, (2007)

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Chantal Ruiz University of Stuttgart

Jörg Desel

Das ist InformatikJ. Desel (Eds.) Springer, (2001)

Das ist InformatikJ. Desel (Eds.) Springer, (2001)Hilfreiche Hilfe Methode, Implementierung und Evaluation eines Verfahrens zur Adaption an das prozedurale WissenD. Iglezakis. Kath. Universität Eichstätt-Ingolstadt, Aachen, (2007)Hilfreiche Hilfe Methode, Implementierung und Evaluation eines Verfahrens zur Adaption an das prozedurale WissenD. Iglezakis. Kath. Universität Eichstätt-Ingolstadt, Aachen, (2007)

Tahsin Deliktas University of Stuttgart

Kontrolle und Identifizierung von Pressteilen im freien Fall : Digitalisierung beim Kaltfließpressen durch Freifallinspektion und -kontrolleT. Deliktas, M. Liewald, P. Clauß, T. Schmid-Schirling, I. Kuntz, M. Feurer, G. Dimitropoulos, F. Wientapper, and F. Räuchle. Werkstattstechnik, 113 (10): 389-394 (2023)

Univ. -Prof. Dr. Gerd de Bruyn University of Stuttgart

Anda Degeratu University of Stuttgart

Other publications of authors with the same name

Static Power Consumption in CMOS Gates Using Independent Bodies.D. Guerrero, A. Millán, J. Juan-Chico, M. Bellido, P. de Clavijo, E. Ostúa, and J. Viejo. PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).A. Millán, J. Juan-Chico, M. Bellido, P. de Clavijo, and D. Guerrero. PATMOS, volume 2451 of Lecture Notes in Computer Science, page 477-486. Springer, (2002)Minimalistic SDHC-SPI hardware reader module for boot loader applications.P. de Clavijo, E. Ostúa, M. Díaz, J. Juan, J. Viejo, and D. Martos. Microelectronics Journal, (2017)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.P. de Clavijo, J. Juan-Chico, M. Bellido, A. Acosta, and M. Valencia. DATE, page 467-471. IEEE Computer Society, (2001)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.J. Viejo, M. Bellido, A. Millán, E. Ostúa, J. Juan, P. de Clavijo, and D. Guerrero. IES, page 1-7. IEEE, (2006)Internode: Internal Node Logic Computational Model.A. Millán, M. Bellido, J. Juan-Chico, D. Guerrero, P. de Clavijo, and E. Ostúa. Annual Simulation Symposium, page 241-248. IEEE Computer Society, (2003)Signal Sampling Based Transition Modeling for Digital Gates Characterization.A. Millán, J. Juan-Chico, M. Bellido, P. de Clavijo, D. Guerrero, and E. Ostúa. PATMOS, volume 3254 of Lecture Notes in Computer Science, page 829-837. Springer, (2004)A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot.A. Carrasco, J. Ropero, P. de Clavijo, J. Benjumea, and A. Luque. QRS Companion, page 633-634. IEEE, (2018)Logic-Level Fast Current Simulation for Digital CMOS Circuits.P. de Clavijo, J. Juan-Chico, M. Díaz, A. Calderón, D. Martos, E. Ostúa, and J. Viejo. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 425-435. Springer, (2005)Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.A. Calderón, M. Díaz, J. Juan-Chico, P. de Clavijo, D. Martos, E. Ostúa, and J. Viejo. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 337-347. Springer, (2005)

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Disambiguation of "de Clavijo, Paulino Ruiz"

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Design of a FFT/IFFT module as an IP core suitable for embedded systems.

Please choose a person to relate this publication to

Chantal Ruiz University of Stuttgart

Jörg Desel

Tahsin Deliktas University of Stuttgart

Univ. -Prof. Dr. Gerd de Bruyn University of Stuttgart

Anda Degeratu University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "de Clavijo, Paulino Ruiz"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design of a FFT/IFFT module as an IP core suitable for embedded systems.

Please choose a person to relate this publication to

Chantal Ruiz University of Stuttgart

Jörg Desel

Tahsin Deliktas University of Stuttgart

Univ. -Prof. Dr. Gerd de Bruyn University of Stuttgart

Anda Degeratu University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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Chicago
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Design of a FFT/IFFT module as an IP core suitable for embedded systems.