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Signal Sampling Based Transition Modeling for Digital Gates Characterization.

A. Millán, J. Juan-Chico, M. Bellido, P. de Clavijo, D. Guerrero, and E. Ostúa. PATMOS, volume 3254 of Lecture Notes in Computer Science, page 829-837. Springer, (2004)

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Juan Vargas University of Stuttgart

Jose Juan Jeronimo Rendon University of Stuttgart

Ph. D. Juan Esteban Martinez Jaramillo University of Stuttgart

Dr. -Ing. Juan Santiago López Bermúdez University of Stuttgart

Juan Patricio Lara Ditzel University of Stuttgart

Other publications of authors with the same name

Improving the Performance of Static CMOS Gates by Using Independent Bodies.D. Guerrero, A. Millán, J. Juan-Chico, M. Díaz, P. de Clavijo, E. Ostúa, and J. Viejo. J. Low Power Electronics, 3 (1): 70-77 (2007)Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.C. Baena, J. Juan-Chico, M. Bellido, P. de Clavijo, C. Jiménez, and M. Valencia. PATMOS, volume 2451 of Lecture Notes in Computer Science, page 353-362. Springer, (2002)Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.P. de Clavijo, J. Juan-Chico, M. Bellido, A. Millán, and D. Guerrero. PATMOS, volume 2451 of Lecture Notes in Computer Science, page 400-408. Springer, (2002)Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.A. Calderón, M. Díaz, J. Juan-Chico, P. de Clavijo, D. Martos, E. Ostúa, and J. Viejo. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 337-347. Springer, (2005)Logic-Level Fast Current Simulation for Digital CMOS Circuits.P. de Clavijo, J. Juan-Chico, M. Díaz, A. Calderón, D. Martos, E. Ostúa, and J. Viejo. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 425-435. Springer, (2005)Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.A. Acosta, R. Jiménez, J. Juan-Chico, M. Bellido, and M. Valencia. PATMOS, volume 1918 of Lecture Notes in Computer Science, page 316-326. Springer, (2000)Static Power Consumption in CMOS Gates Using Independent Bodies.D. Guerrero, A. Millán, J. Juan-Chico, M. Bellido, P. de Clavijo, E. Ostúa, and J. Viejo. PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).A. Millán, J. Juan-Chico, M. Bellido, P. de Clavijo, and D. Guerrero. PATMOS, volume 2451 of Lecture Notes in Computer Science, page 477-486. Springer, (2002)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.P. de Clavijo, J. Juan-Chico, M. Bellido, A. Acosta, and M. Valencia. DATE, page 467-471. IEEE Computer Society, (2001)Accurate Logic-Level Current Estimation for Digital CMOS Circuits.P. de Clavijo, J. Juan-Chico, M. Díaz, A. Millán, D. Guerrero, E. Ostúa, and J. Viejo. J. Low Power Electronics, 2 (1): 87-94 (2006)