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Minimalistic SDHC-SPI hardware reader module for boot loader applications., , , , , and . Microelectronics Journal, (2017)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model., , , , and . DATE, page 467-471. IEEE Computer Society, (2001)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , and . IES, page 1-7. IEEE, (2006)Static Power Consumption in CMOS Gates Using Independent Bodies., , , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)., , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 477-486. Springer, (2002)Internode: Internal Node Logic Computational Model., , , , , and . Annual Simulation Symposium, page 241-248. IEEE Computer Society, (2003)Signal Sampling Based Transition Modeling for Digital Gates Characterization., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 829-837. Springer, (2004)A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot., , , , and . QRS Companion, page 633-634. IEEE, (2018)Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation., , , , and . IEEE Trans. Instrumentation and Measurement, 60 (12): 3961-3963 (2011)Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies., , , , , and . J. Low Power Electronics, 6 (1): 93-102 (2010)