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Disambiguation of "Viejo, Julian"

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Improving the Performance of Static CMOS Gates by Using Independent Bodies.

, , , , , , and . J. Low Power Electronics, 3 (1): 70-77 (2007)

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Julian Schöpf University of Stuttgart

Julian Dinkelacker University of Stuttgart

Julian Scholl University of Stuttgart

Julian Fischer University of Stuttgart

Julian Beyer University of Stuttgart

 

Other publications of authors with the same name

Improving the Performance of Static CMOS Gates by Using Independent Bodies., , , , , , and . J. Low Power Electronics, 3 (1): 70-77 (2007)Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation., , , , and . IEEE Trans. Instrumentation and Measurement, 60 (12): 3961-3963 (2011)Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies., , , , , and . J. Low Power Electronics, 6 (1): 93-102 (2010)Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates., , , , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 337-347. Springer, (2005)Logic-Level Fast Current Simulation for Digital CMOS Circuits., , , , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 425-435. Springer, (2005)Network Time Synchronization: A Full Hardware Approach., , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 225-234. Springer, (2012)Design of a FFT/IFFT module as an IP core suitable for embedded systems., , , , , , , and . SIES, page 337-340. IEEE, (2007)Accurate Logic-Level Current Estimation for Digital CMOS Circuits., , , , , , and . J. Low Power Electronics, 2 (1): 87-94 (2006)Design and implementation of a suitable core for on-chip long-term verification., , , , , and . SIES, page 234-237. IEEE, (2010)Long-term on-chip verification of systems with logical events scattered in time., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (5): 402-408 (2012)