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Disambiguation of "Millán, Alejandro"

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Design of a FFT/IFFT module as an IP core suitable for embedded systems.

, , , , , , , and . SIES, page 337-340. IEEE, (2007)

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Alejandro Tristan Jimenez University of Stuttgart

Alejandro Gabriel Villanueva Zacarias

Dr. Pablo Alejandro Mora Pinto University of Stuttgart

 

Other publications of authors with the same name

Static Power Consumption in CMOS Gates Using Independent Bodies., , , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)., , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 477-486. Springer, (2002)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , and . IES, page 1-7. IEEE, (2006)Fast Hardware Implementations of Static P Systems., , , , and . Comput. Informatics, 35 (3): 687-718 (2016)Improving the Performance of Static CMOS Gates by Using Independent Bodies., , , , , , and . J. Low Power Electronics, 3 (1): 70-77 (2007)Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level., , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 400-408. Springer, (2002)Internode: Internal Node Logic Computational Model., , , , , and . Annual Simulation Symposium, page 241-248. IEEE Computer Society, (2003)Signal Sampling Based Transition Modeling for Digital Gates Characterization., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 829-837. Springer, (2004)Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation., , , , and . IEEE Trans. Instrumentation and Measurement, 60 (12): 3961-3963 (2011)Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies., , , , , and . J. Low Power Electronics, 6 (1): 93-102 (2010)