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A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2015)The Murchison Widefield Array: Design Overview., , , , , , , , , and 38 other author(s). Proc. IEEE, 97 (8): 1497-1506 (2009)12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%., , , , , , , , , and 3 other author(s). ISSCC, page 212-213. IEEE, (2017)Online Data Visualization of Multidimensional Databases Using the Hilbert Space-Filling Curve., and . VIEW, volume 4370 of Lecture Notes in Computer Science, page 92-109. Springer, (2006)Isolated Preset Architecture for a 32nm SOI embedded DRAM macro., , , , , , and . VLSIC, page 110-111. IEEE, (2012)An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems., , , and . IEEE Trans. Computers, 44 (11): 1306-1317 (1995)Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (10): 1558-1571 (2012)Trace alignment algorithms for offline workload analysis of heterogeneous architectures., , , , and . ICCAD, page 654-661. IEEE, (2013)Energy Efficient Architecture for Graph Analytics Accelerators., , , , , , and . ISCA, page 166-177. IEEE Computer Society, (2016)