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Energy Efficient Architecture for Graph Analytics Accelerators.

, , , , , , and . ISCA, page 166-177. IEEE Computer Society, (2016)

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Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (1): 84-95 (2008)A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (12): 2784-2794 (2006)Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (3): 381-394 (2015)Two-layer bus routing for high-speed printed circuit boards., and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 213-227 (2006)Escape Routing For Dense Pin Clusters In Integrated Circuits.. DAC, page 49-54. IEEE, (2007)Gate sizing and device technology selection algorithms for high-performance industrial designs., , and . ICCAD, page 724-731. IEEE Computer Society, (2011)Optimal routing algorithms for pin clusters in high-density multichip modules., , and . ICCAD, page 767-774. IEEE Computer Society, (2005)Algorithms for simultaneous escape routing and Layer assignment of dense PCBs., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (8): 1510-1522 (2006)Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms.. ISPD, page 39. ACM, (2019)An improved benchmark suite for the ISPD-2013 discrete cell sizing contest., , , , , and . ISPD, page 168-170. ACM, (2013)