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Disambiguation of "Plass, Donald W."

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17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.

, , , , , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Tim W{\"{u}}rtele

Tim W{\"{u}}rtele

Kent W. Stewart

Tim W{\"{u}}rtele

Univ. -Prof. Dr. -Ing. Wolfgang Rheinheimer University of Stuttgart

 

Other publications of authors with the same name

Design of the Power6 Microprocessor., , , , , , , , , and 7 other author(s). ISSCC, page 96-97. IEEE, (2007)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth., , , , , , , , , and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)IBM POWER8 circuit design and energy optimization., , , , , , , , , and 13 other author(s). IBM Journal of Research and Development, (2015)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)IBM POWER6 SRAM arrays., and . IBM Journal of Research and Development, 51 (6): 747-756 (2007)5.5GHz system z microprocessor and multi-chip module., , , , , , , , , and 13 other author(s). ISSCC, page 46-47. IEEE, (2013)A 5.2GHz microprocessor chip for the IBM zEnterprise™ system., , , , , , , , , and 17 other author(s). ISSCC, page 70-72. IEEE, (2011)Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics., , , , , and . J. Solid-State Circuits, 44 (3): 965-976 (2009)IBM z13 circuit design and methodology., , , , , , , , , and 22 other author(s). IBM Journal of Research and Development, (2015)A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)