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Discrete time cellular neural networks.. Technical University Munich, Germany, (1992)First- and second-level packaging of the z990 processor cage., , , , , , , and . IBM Journal of Research and Development, 48 (3-4): 379-394 (2004)Electronic packaging of the IBM System z196 enterprise-class server processor cage., , , , , , , , , and 7 other author(s). IBM Journal of Research and Development, 56 (1): 2 (2012)5.5GHz system z microprocessor and multi-chip module., , , , , , , , , and 13 other author(s). ISSCC, page 46-47. IEEE, (2013)Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module., , , , , , , , , and 15 other author(s). J. Solid-State Circuits, 49 (1): 9-18 (2014)Packaging design challenges of the IBM System z10 Enterprise Class server., , , , , , , , , and 1 other author(s). IBM Journal of Research and Development, 53 (1): 10 (2009)First- and second-level packaging for the IBM eServer z900., , , , , , , , and . IBM Journal of Research and Development, 46 (4-5): 397-420 (2002)On the convergence of discrete-time neural networks., , and . I. J. Circuit Theory and Applications, 21 (2): 191-195 (1993)An analog implementation of discrete-time cellular neural networks., , and . IEEE Trans. Neural Networks, 3 (3): 466-476 (1992)Electronic packaging of the IBM z13 processor drawer., , , , , , , , and . IBM Journal of Research and Development, (2015)